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Low-Cost, Crystal-Based, Programmable,
ASK/FSK Transceiver with Fractional-N PLL
Table 15. On-Timer (t ON ) Configuration
MIN t ON
MAX t ON
ONPS1
ONPS0
t ON TIME BASE
REG 0x0B = 0x00
REG 0x0B = 0xFF
REG 0x0C = 0x01
REG 0x0C = 0xFF
0
0
1
1
0
1
0
1
120μs
480μs
1920μs
7680μs
120μs
480μs
1.92ms
7.68ms
7.86s
31.46s
2min 6s
8min 23s
On Timer (t ON )
The on timer, t ON (see Figure 10), is a 16-bit timer that
is configured through register 0x0B for the upper byte,
register 0x0C for the lower byte (Table 15). The infor-
mation stored in this timer provides an additional way to
control the duration of the on time of the receiver.
The CPU must begin driving DIO low any time during
t LOW = t CPU + t RF + t ON . If the CPU fails to drive DIO
low at the end of t ON , DIO is pulled high through the
internal pullup resistor and the time sequence is restart-
ed, leaving the MAX7032 powered down. Any time the
DIO line is driven high while the DRX = 1, the DRX
sequence is initiated, as defined in Figure 10. In the
event that the CPU is processing data, after t ON
expires, the CPU should keep the MAX7032 awake by
holding the DIO line low.
The data written to the t ON register (register 0x0B and
register 0x0C) are multiplied by the t ON time base
(Table 15) to give the total t ON time. See the example in
the Off Timer (t OFF ) section. On power-up, the on-timer
register is reset to zero and must be written before
using DRX mode.
Transmitter Low-Frequency Register (TxLOW)
The TxLOW register sets the divider information of the
fractional-N synthesizer for the lower transmit frequency
in FSK mode. See the example given in the Fractional-N
PLL section. In ASK mode, TxLOW determines the carri-
er frequency.
Transmitter High-Frequency Register (TxHIGH)
The TxHIGH register sets the divider information of the
fractional-N synthesizer for the upper transmit frequency
in the FSK mode. In ASK mode, the content of TxHIGH
is not used. The 16-bit register contains the binary rep-
resentation of the TX PLL divider ratio, which is shown in
the example in the Fractional-N PLL section.
Applications Information
Output Matching to 50 Ω
When matched to a 50 Ω system, the MAX7032’s PA is
capable of delivering +10dBm of output power at V DD
= +2.7V. The output of the PA is an open-drain transis-
tor that requires external impedance matching and
pullup inductance for proper biasing. The pullup induc-
tance from the PA to PAV DD serves three main purpos-
es: it resonates the capacitive PA output, provides
biasing for the PA, and becomes a high-frequency
choke to prevent RF energy from coupling into V DD .
The network also forms a bandpass filter that provides
attention for the higher order harmonics.
Output Matching to PCB Loop Antenna
In most applications, the MAX7032 must be impedance
matched to a small-loop antenna. The antenna is usual-
ly fabricated out of a copper trace on a PCB in a rec-
tangular, circular, or square pattern. The antenna has
an impedance that consists of a lossy component and
a radiative component. To achieve high radiating effi-
ciency, the radiative component should be as high as
possible, while minimizing the lossy component. In
addition, the loop antenna has an inherent loop induc-
tance associated with it (assuming the antenna is termi-
nated to ground). For example, in a typical application,
the radiative impedance is less than 0.5 Ω , the lossy
impedance is less than 0.7 Ω , and the inductance is
approximately 50nH to 100nH.
Layout Considerations
A properly designed PCB is an essential part of any
RF/microwave circuit. On high-frequency inputs and
outputs, use controlled-impedance lines and keep
them as short as possible to minimize losses and radia-
tion. At high frequencies, trace lengths that are on the
order of λ /10 or longer act as antennas, where λ is the
wavelength.
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